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STLC5048
FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
s s s s s
s s s s s s s s s s s s s
FULLY PROGRAMMABLE MONOLITHIC 4 CHANNEL CODEC/FILTER SINGLE +3.3V SUPPLY A/m LAW PROGRAMMABLE LINEAR CODING (16 BITS) OPTION PCM HIGHWAY FORMAT AUTOMATICALLY DETECTED:1.536 or 1.544 MHz2.048, 4.096, 8192 MHz TWO PCM PORTS AVAILABLE TX GAIN PROGRAMMING: 33dB RANGE; <0.01dB STEP RX GAIN PROGRAMMING:42dB RANGE; <0.01dB STEP PROGRAMMABLE SLIC INPUT IMPEDANCE PROGRAMMABLE TRANSHYBRID BALANCE FILTER PROGRAMMABLE EQUALIZATION (FREQUENCY RESPONSE) PROGRAMMABLE TIME SLOT ASSIGNMENT DIGITAL AND ANALOG LOOPBACKS SLIC CONTROL PORTSTATIC (16 I/Os) DYNAMIC (12 I/Os + 4 CS) BUILT-IN TEST MODE WITH TONE GENERATION, MCU ACCESS TO PCM DATA 64 TQFP (10X10mm) PACKAGE PROGRAMMABLE SLIC LINE CURRENT LIMITATION PROGRAMMABLE SLIC OFF-HOOK DETECTION THRESHOLD
TQFP64 (10x10mm) ORDERING NUMBER: STLC5048
buffer driving the SLIC RX input and on an amplifier input stage normally driven by the SLIC TX output. Due to the single supply voltage a midsupply reference level is generated internally by the device and all analog signals are referred to this level (AGND). The PCM interface uses one common 8KHz frame sync. pulse for transmit and receive direction. The bit clock is automatically detected between four standards: 1.563/1.544MHz, 2.048MHz, 4.096MHz, 8192MHz. Two PCM port are provided: the channels can be connected to port A or/and B. Device programmability is achieved by means of several registers and commands allowing to set the different parameters like TX/RX gains, line impedance, transhybrid balance, equalization (frequency response), encoding law (A/), time slot assignment, independent channels power up/down, loopbacks, PCM bits offset. The STLC5048 can be programmed via serial interface running up to 8 MHz. One interrupt output pin is also provided. A GUI interface is also available to emulate and program the coefficients for impedance synthesis, echo cancelling and channel filtering.
DESCRIPTION The STLC5048 is a monolithic fully programmable 4 channel CODEC and filter. It operates with a single +3.3V supply. The analog interface is based on a receive output
January 2003
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STLC5048
BLOCK DIAGRAM
VCC VEE VDD VSS SUB CAP M1 M0
ANALOG FRONT END
DIGITAL PROCESSOR
PCM INTERFACE
FS MCLK DRA DRB DXA DXB TSXA COEFF BUS
VFRO0 GR0
D/A CH0
16 16 A/U LAW ENCODER
VFX10 GX0
A/D CH0
PLL BLOCK
A/U LAW DECODER DATA INTERFACE CONTROL INTERFACE
TSXB IO11 IO10 IO9 IO8 IO7 IO6 IO5 SLIC INTERFACE IO4 IO3 IO2 IO1
VFRO1 GR1
D/A CH1 8 SHAPPIRE MACRO 8 INTERPOLAT. DECIMATORS KD FILTERS
VFX11 GX1
A/D CH1
VFRO2 GR2
D/A CH2 BIAS GENER. A/D CH2 GX2 to analog FE D/A CH3 GR3 A/D CH3 GX3 SLIC THR SERIAL INTERFACE CONFIG. REGISTERS CONTROLLER
IO0 CS3 CS2 CS1 CS0 INT
VFX12
VFRO3
CCLK CI CO CS
VFX13
ITH
ILIM
VBG
D00TL467
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VDIN VAin TSTG TLEAD VCC to VEE VDD to VSS Digital Input Pin Voltage Analog Input Pin Voltage(VDD=VCC; VEE=VSUB) Storage Temperature Range Lead Temperature (soldering, 10s) Parameter Value 4.6 4.6 5.5 VCC + 0.5; VEE - 0.5 -65 to +150 300 Unit V V V V C C
OPERATING RANGE
Symbol VCC , VDD TOP Supply Voltage Operating Temperature Range Parameter Value 3.3 +/- 5% -40 to +85 Unit V C
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-Ambient Value 70 Unit C/W
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STLC5048
PIN CONNECTION (Top view)
VCC4
VEE4
VEE2
RES.
VEE3
CS2_
CS3_
IO10
IO11
N.C.
IO6
IO7
IO8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 N.C. N.C. INT CS CO CI CCLK VSS VDD DRA DXA TSXA MCLK FS DXB DRB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO3 IO4 IO5 VCC5 VEE5 M0 CS0_ CS1_ VEE1 VEE0 TSXB_ RES N.C. IO0 IO1 IO2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VFRO3 ILIM VFXI3 VCC3 VCC2 VFXI2 VFRO2 SUB CAP VFRO1 VFXI1 VCC1 VCC0 VFXI0 ITH VFRO0
VBG
D94TL150
IO9
PIN DESCRIPTION I/O DEFINITION
Type AI AO ODO DI DO DIO DTO DPS APS Analog Input Analog Output Open Drain Output Digital Input Digital Output Digital Input / Output Digital Tristate Output Digital Power Supply Analog Power Supply Definition
M1
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STLC5048
PIN DESCRIPTION (continued) ANALOG PIN DESCRIPTION
No. 33 Name VFRO0 Type AO Description Receive analog amplifier output channel 0. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output. Receive analog amplifier output channel 1. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output. Receive analog amplifier output channel 2. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output. Receive analog amplifier output channel 3. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output. TX Input Amplifier channel 0. Typ 1M input impedance TX Input Amplifier channel 1. Typ 1M input impedance TX Input Amplifier channel 2. Typ 1M input impedance TX Input Amplifier channel 3. Typ 1M input impedance AGND Voltage filter pin: a 100nF capacitor must be connected between ground and this pin. AO AO AI SLIC Off Hook detection threshold. SLIC line current limitation. SLIC VBG reference for DC characterisrics programmability.
39
VFRO1
AO
42
VFRO2
AO
48
VFRO3
AO
35 38 43 46 40 34 47 49
VFXI0 VFXI1 VFXI2 VFXI3 CAP ITH ILIM VBG
AI AI AI AI
NOT CONNECTED
2, 18, 63, 1 32, 64 N.C. RES Not Connected, must be left open Reserved pins, must be connected to ground
POWER SUPPLY PIN DESCRIPTION
25,36, 37,44, 45,56 26,30, 31,50, 51,55 9 8 41 VCC0..5 APS Total 6 pins: 3.3V analog power supplies, should be shorted together, require 100nF decoupling capacitor to VEE. Total 6 pins: analog ground, should be shorted together.
VEE0..5
APS
VDD VSS SUB
DPS DPS DPS
Digital Power supply 3.3V, require 100nF decoupling capacitor to VSS. Digital Ground. Substrate connection. Must be shorted together with VEE and VSS pins.
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STLC5048
PIN DESCRIPTION (continued) DIGITAL PIN DESCRIPTION
No. 27 54 Name M0 M1 Type DI Mode Select. M1 M0 0 0 1 0 0 1 1 1 Description Mode select Reset Status Normal Operation Not Allowed Not Allowed
14
FS
DI
Frame Sync. Pulse. A pulse or a square waveform with an 8kHz repetition rate is applied to this pin to define the start of the receive and transmit frame. Effective start of the frame can be then shifted of up to 7 clock pulses independently in receive and transmit directions by proper programming of the PCMSH register. Master Clock Input. Four possible frequencies can be used: 1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz. The device automatically detect the frequency applied. This signal is also used as bit clock and it is used to shift data into and out of the DRA/B and DXA/B pins. Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance state except when a time slot is active on the DXA output. In this case TSXA output pulls low to enable the backplane line driver. Transmit PCM interface A. It remains in high impedance state except during the assigned time slots during which the PCM data byte is shifted out on the rising edge of MCLK. Receive PCM interface A. It remains inactive except during the assigned receive time slots during which the PCM data byte is shifted in on the falling edge of MCLK. General control I/O pin #5. Can be programmed as input or output via DIR register. Depending on content of CONF register can be a static input/output or a dynamic input/output synchronised with the CSn output signals controlling the SLICs. General control I/O pin #6. (see IO5 description). General control I/O pin #7. (see IO5 description). General control I/O pin #8. (see IO5 description). General control I/O pin #9. (see IO5 description). General control I/O pin #10. (see IO5 description). General control I/O pin #11. (see IO5 description). General control I/O pin #0. (see IO5 description). General control I/O pin #1. (see IO5 description). General control I/O pin #2. (see IO5 description). General control I/O pin #3. (see IO5 description). General control I/O pin #4. (see IO5 description).
13
MCLK
DI
12
TSXA
ODO
11
DXA
DTO
10
DRA
DI
24
IO5
DIO
62 61 60 59 58 57 19 20 21 22 23
IO6 IO7 IO8 IO9 IO10 IO11 IO0 IO1 IO2 IO3 IO4
DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO
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STLC5048
PIN DESCRIPTION (continued) DIGITAL PIN DESCRIPTION (continued
No. 28 Name CS0 Type DIO Description Slic CS control #0. Depending on CONF reg. content can be a CS output for SLIC #0 or a static I/O. When configured as CS output it is automatically generated by the CODEC with a repetition time of 31.25ms. In this mode also the IO0..11 are synchronised and carry proper data in and out synchronous with CS. When configured as static I/O, the direction is defined by CSDIR register content. Slic CS control #1, (see CS0 description). Slic CS control #2, (see CS0 description). Slic CS control #3, (see CS0 description). Chip Select Input, when this pin is low control information can be written to or read from the device via the CI and CO pins. Clock of Serial Control Bus. This clock shifts serial control information into or out of CI or CO when CS input is low depending on the current instruction. CCLK may be asynchronous with the other system clocks. Control Data Input of Serial Control Bus. Control data is shifted in the device when CS is low and clocked by CCLK. Depending on the addressed register different numbers of consecutive bytes can be loaded. Control Data Output of Serial Control Bus. Control data is shifted out the device when CS is low and clocked by CCLK. Depending on the addressed register different numbers of consecutive bytes can be shifted out. Interrupt output (open drain), goes low when a data change has been detected in the I/O pins or another interrupt source is active. One mask register allows to mask any I/O pin. Interrupt is reset when the I/ O register is read. Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance state except when a time slot is active on the DXB output. In this case TSXB output pulls low to enable the backplane line driver. Transmit PCM interface B. It remains in high impedance state except during the assigned time slots during which the PCM data byte is shifted out on the rising edge of MCLK. Receive PCM interface B. It remains inactive except during the assigned receive time slots during which the PCM data byte is shifted in on the falling edge of MCLK.
29 53 52 4 7
CS1 CS2 CS3 CS CCLK
DIO DIO DIO DI DI
6
CI
DI
5
CO
DI
3
INT
ODO
17
TSXB
ODO
15
DXB
DTO
16
DRB
DI
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STLC5048
FUNCTIONAL DESCRIPTION The STLC5048 is a fully programmable device with embedded ROM and RAM. The ROM is used to contain the default state coefficients for the programmable filters, while the RAM is used to load the desired coefficient values. POWER ON INITIALIZATION When power is first applied it is recommended to reset the device (M1=M0=0) in order to set all the internal registers to the reset value (see register description); this means also power down mode for all the four channels and SW reset bit (RES) set in the CONF register. When the RES bit is set, the only instructions allowed are the one that disable this bit and the REACOM instruction: all other instructions are ignored. It is not possible to disable the RES bit and write the other bits of the CONF register with the same instruction. Of course, RESET mode can be programmed also by writing the RES bit of the CONF register. See appendix C for the power up sequence. During RESET condition all the I/On and CSn pins are set as inputs, DX is in high impedance and all VFROn are set to AGND. After the reset all registers are loaded with the reset value. It means that the PCM interface and all the VFRO outputs are configured as described in the Power Down State, while no transmit or receive time slot are set. Then, filters and gain blocks are configured with the coefficient defined in the Default State. POWER DOWN STATE Each of the four channel may be put into power down mode by setting the appropriate bit in the CONF register. In this mode the eventual programmed DX channel is set in high impedance while the VFRO outputs are forced to AGND. When all the channels are set in Power Down mode the device enters the Power Down state: all the blocks related to the data processing are turned off, while the RAM is On or Off according to the PDR bit value in the COMEN register.
Figure 1. Block Diagram of a single channel.
*
DR A/mu HPR R GR
*
LPR D/A
RX
*
VFRO
*
B Z
*
*
KD
*
KA
*
DX A/mu HPX X GX
*
LPX A/D TX
*
VFXI
* PROGRAMMABLE BLOCKS
D00TL468
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STLC5048
FUNCTIONAL DESCRIPTION (continued) RINGING STATE This state can be used during the ringing phase in order to transmit a low frequency ringing signal (25-50 Hz). In order to obtain a 1 Vrms ringing signal at VFRO output a digital signal DR equal to -0.78dBm0 must be provided. This state means B, Z, X, KD and KA blocks equal to open circuits and the R block configured in order to obtain the maximum gain at the frequency of 25-50 Hz. During the ringing state if the TX time slot is enabled the idle PCM code is forced to DX. To switch to this state, a bit (FR0..3) in the COEFST register must be set for every channel. The programmed values for the previous blocks become active only when the FR and FD bits are reset. If both FR and FD bits of a channel are set, the selected coefficient will be those of the Ringing State. IMPEDANCE SYNTHESYS The impedance synthesis is performed by fully digital filters (Z and KD) and by an analog path (KA). The Z, KD and KA filters report to the receive path the feedback signal coming from the transmit path. The coefficients of the Z, KD and KA filters are programmed via the ZFC, KD and AFE_CFF commands respectively. ECHO CANCELING The trans-hybrid balance is performed by the digital programmable filter B. The B filter reports to the transmit path the signal coming from the receive path. The coefficient of the B filter are programmed via the BFC command. Figure 2. Transmit path.
TXG VFXI 1M AGND for TXG=0dB; GX=0dB (FF) 61mVms => 0dBm0
D00TL469
CONV.
GXO
GX
A/
DX
TRANSMIT PATH The transmit section input consist of the input amplifier, the A/D converter, the equalization filter X, the gain block GX, the encoder and the channel filters (LPX and HPX). The input amplifier is provided of a programmable gain with a typical input impedance of 1M. The amplifier gain can be programmed with two different values (0dB, +3.52dB) by means of the TXG Register. VFXI input must be AC coupled to the signal; the voltage swing allowed is 1.4Vpp when the preamplifier gain is set to 0dB and 0.93Vpp when the gain is 3.52dB; higher levels must be reduced through proper dividers. Following the input amplifier the signal is converted into digital domain and a X filter block is programmed to equalise together with the HPX and LPX filters the frequency response. The coefficients of the X filter are programmed via the XFC command. A gain block (GX) allows to set the transmit level in a 30dB range, with steps <0.01dB. This block can be programmed via the GTX command.
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STLC5048
FUNCTIONAL DESCRIPTION (continued) The needed TX gain can be set by proper programming of the GX block in combination with the TX amplifier. Setting GTX=00h, the transmitted signal is muted and an idle PCM signal is generated on DX. Concerning the CODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition, via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits). In this case the signal sent on the DX will take two adjacent PCM channels, proper care has to be taken in the time slot selection programming (DXTS register). The intrinsec non programmable gain GX0 set the TX path gain to 22.07dB. The absolute gain level (see electrical characteristics) refers to this intrinsec gain. RECEIVE PATH The receive path of the STLC5048 consists of the decoder section, the gain block GR, the R filter, the channel filters (LPR, HPR) the D/A converter and the output amplifier. Concerning the DECODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits). In this case the signal received on the DR input will take two adjacent PCM channels, proper care has to be taken in the time slot selection programming (DRTS register). The gain block GR is controlled by the GRX command allowing 30dB gain range in 0.01dB steps. The R filter together the channel filters (LPR and HPR) performs the line equalization. The coefficients of the R filter are programmed via the RFC command. The signal is converted in the analog domain and amplified by the RX amplifier that can be programmed with four different values (mute, 0dB, -6dB and -12dB) by means of RXG register. Figure 3. Receive path.
RXG DR A/ GR GRO CONV. VFRO
D00TL470
for RXG=0dB; GR=0dB 0dBm0 => -3dBm/600
VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent a DC current flow. In order to get the best noise performances it is recommended to keep GRX value as close as possible to the maximum (FFh) setting properly the additional attenuation by means of RXG. The intrinsec non programmable gain GR0 set the RX path gain to -3.15dB. The absolute gain level (see electrical characteristics) refers to this intrinsec gain. PCM INTERFACE The STLC5048 dedicates eight pins to the interface with the PCM highways. MCLK represents the bit clock and is also used by the device as a source for the clock of the internal PLL. Five possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating fre9/45
STLC5048
quency is automatically detected by the device the first time both MCLK and FS are applied and becomes active after the second FS period. MCLK synchronises both the transmit data (DXA/B) and the receive data (DRA/B). The Frame Sync. signal FS is the common time base for all the four channels. Transmit and Receive programmable Time-Slots are framed by an internal sync. signal that can be coincident with FS or delayed of 1 or 7 MCLK cycles depending on the programming of PCMSH register. Two PCM ports are available: every channel can be connected to a different PCM port by means of PCMCOM register. DXA/B represents the transmit PCM interface. It remains in high impedance state except during the assigned time slots during which the PCM data byte is shifted out on the rising/falling edge of MCLK according to the TE bit of PCMCOM register. The four channels can be shifted out in any possible timeslot as defined by the DXTS registers. The assigned Time Slot (Transmit and Receive) takes place in the 8 MCLK cycles following the rising edge of FS. The data can be shifted out on port A and/or B according to PCMCOM register. If one CODEC is set in Power Down by software programming the corresponding time slot is set in High Impedance. When linear coding mode is selected by CONF register programming the output channel will need two consecutive time slots (see register description). DRA/B represents the receive PCM interface. It remains inactive except during the assigned time slots during which the PCM data byte is shifted in on the falling edge of MCLK. The four channels are shifted in any possible time slot as defined by the DRTS registers. If one Codec is set in Power Down by software programming the corresponding time slot is not loaded and the VFRO output is kept at steady AGND level. INSTRUCTION BYTE STRUCTURE
First Byte (Address or command ID) 7 R/W 6 I6 5 I5 4 I4 3 I3 2 I2 1 I1 0 I0 7 D7 6 D6 Following Bytes (Data) 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
R/W=0: Write Operation R/W=1: Read Operation I6..I0: Instruction Identifier: it can be a register address or a command identifier. The number of data bytes depends on the instruction type. The first bit of a byte is the MSB, the first byte of an instruction is the LSByte.
When linear coding mode is selected by CONF register programming the input channel will need two consecutive time slots (see register description). The data can be shifted in from port A or B according to the PCMCOM register. TSXA/B represents the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance state except when a time slot is active on the DXA/B output. In this case TSXA/B output pulls low to enable the backplane line driver. Should be strapped to VSS when not used. Finally by means of the LOOPB register it is possible to implement a digital or analog loopback on any of the selected channels. MCU CONTROL INTERFACE The MCU serial control interface consists of 4 pins. CCLK: Control Clock CI: CO: CS: Serial Data In Serial Data Out Chip Select Input
Control instructions require at least two bytes: however two single byte instructions are also provided.
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STLC5048
In the multiple byte instructions the first one specifies the command or the register address and the access type (Read or Write). The following bytes contain the data to be loaded into the internal RAM (on CI wire) or carry out the RAM content (on CO wire) depending on the R/W bit of the first byte. CO wire is normally in High Impedance and goes to low impedance only after the first byte in case of Read operation. This allows to use a common wire for both CI/CO. CS, normally High, is set Low during the transmission/reception of a byte, lasting 8 CCLK pulses. Between two consecutive access the CS must be set high. The CCLK can be a continuos or a gated clock. The result of any instruction (read/write operation), if negative, can generate an interrupt (maskable). The interrupt register (INT) contains the cause information of the generated interrupt and it is cleared every time that it is read. Depending on the instruction specified in the first byte, the STLC5048 waits a defined number of data bytes. If the STLC5048 doesn't receive the data byte within a predefined period specified by means of T_OUT command, an internal time out rejects the instruction. The time-out time is verified between two consecutive MCU interface access (between the falling edge of the CS and the following rising edge). This feature is used to verify the synchronisation of the MCU interface: however it can be disabled if not desired (see T_OUT reg description). To check this synchronisation is provided a specific register (SYNCK) that returns always a predefined value: if the returned value is different the MCU interface is in out of sync state (the device is waiting a data byte while the MCU is writing an address or vice versa). In this case, it is possible to realign it by means of the execution of a specific single byte instruction (REACOM) from 1 to 53 times, depending on the instructions. Every time an illegal operation (access to not allowed address, time-out violation or clock pulse different than 8 inside a CS active) is performed the MCU interface is put on an error state: to resume it from this state a single REACOM instruction can be used. Anyway after a REACOM instruction a successful SYNC instruction guarantees the correct synchronisation. One additional wire provided to the control interface is an open drain interrupt output (INT) that goes low when a change of status is detected on the I/O pins or other interrupt source are active (see INT register). INT is automatically reset after reading of the register corresponding the cause that has generated the interrupt (see INT register description). A particular register (COMEN) allows to enable a command on different channel at the same time. Every time a command operation is performed at least one channel must be enabled in this register. This feature is useful when all channels must be configured in the same condition. When a command is used to perform a read operation only one channel can be enabled at the same time. To check the configuration of the device a checksum value is provided. This value is calculated on all coefficient parameters entered (coefficients of KD, AFE_CFF, GRX, GTX, RFC, XFC, BFC, ZFC blocks; see CKSUM register description). Two commands are required to get this value: the first one (CKSTART) starts the internal checksum calculation, the second one (CKSUM) returns the calculated value. Between this two commands no other operation are allowed. The checksum value is available within 400us the CKSTART command. Coefficient checksum is defined by this algorithm: X16 + X12 + X5 + 1 This algorithm guarantees a fault coverage of 1 - 2 -16. PROGRAMMING THE DEVICE After the power up, the filters and gain blocks can be programmed also with all the channels set in Power Down. In this case the PDR bit of the COMEN register must be set to 0. With the proper setting of the COMEN register, the commands can be applied to more than one channel at the same time. To read the coefficient values loaded in the RAM, only one channel per time must be enabled in the COMEN register.
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STLC5048
SLIC CONTROL INTERFACE The device provides 12 I/O pins plus 4 CS signals. The interface can work in dynamic or static mode: it can be selected by means of STA bit of the CONF register. s Dynamic Mode: the I/O pins are configured as input or output by means of DIR register. The CS signals are used to select the different SLIC interface. In this case the I/O pin can be multiplexed. The data loaded from SLIC #n via I/O pins configured as input can be read in the DATAn register. The data written in a DATAn register will be loaded on the I/O pins configured as output when the Csn signal will be active.
s
Static Mode: The CS signal can be used as I/O pins. They can be configured as input or output I/O by means of DATA1 register. The data corresponding to the CS signal can be read or written by means of DATA2 register. All data related to the other I/O pins can be read or written by means of DATA0 register.
DC SLIC PROGRAMMABILITY Three additional pins are used to select the On-Hook/Off-Hook detection threshold and the line card limitation of the STLC3080 SLIC. This two values are programmed by ILIM and ITH registers. The programmation of these two registers must be done before the filter coefficients download. The VBG input pin must be connected to the IREF pin of the STLC3080. When the L3235N is used in kit with STLC5048 the ILIM, ITH and VBG pin must be not connected. BUILT IN TEST By means of TONEG register it is possible to inject a tone of variable frequency (25Hz, 1 and 3KHz) and 0dBm0 amplitude into the receive path, replacing any signal coming from the PCM interface. This test can be performed on every channel. Setting the proper bit of the PCMCOM register is also possible to read/write the PCM data coming from the transmit path via the MCU interface (PCMRD/PCMWD registers). This feature can be enabled only on one channel per time. These two features can be used to test the line interface operation. REGISTER ADDRESSES
Addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 10h Name DIR-L DIR-H DATA0-L DATA0-H DATA1-L DATA1-H DATA2-L DATA2-H DATA3-L DATA3-H PCHK-A PCHK-B INT I/O Direction (bit 7-0) I/O Direction (bit 11-8) I/O Data ch#0 (bit 7-0) I/O Data ch #0 (bit 11-8) I/O Data ch#1 (bit 7-0) I/O Data ch #1 (bit 11-8) I/O Data ch#2 (bit 7-0) I/O Data ch #2 (bit 11-8) I/O Data ch#3 (bit 7-0) I/O Data ch #3 (bit 11-8) Persistency Check Time for input A Persistency Check Time for input B Interrupt register Description
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REGISTER ADDRESSES (continued)
11h 12h Addr 13h 14h 20h 21h 23h 25h 26h 27h 2Ah 2Bh 2Ch 2Dh 2Eh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 60h 61h 70h 71h DMASK-L DMASK-H Name IMASK ALARM CONF COMEN SYNCCK CTRLACK CKSUM-L CKSUM-H LOOPB TXG RXG ILIM ITH PCMSH PCMCOM DXTS0 DXTS1 DXTS2 DXTS3 DRTS0 DRTS1 DRTS2 DRTS3 PCMWD-L PCMWD-H PCMRD-L PCMRD-H PCMCTRL TONEG COEFST SWRID HWRID Interrupt Mask reg. Alarm register Configuration register Command Enable reg. Synchronous Check reg. DSP status register Cheksum register L Cheksum register H Loopback register Transmit preamp. Gain Receive preamp. Gain SLIC line current lim. SLIC Off-Hook threshold PCM Shift register PCMCOM register Transmit Timeslot ch #0 Transmit Timeslot ch #1 Transmit Timeslot ch #2 Transmit Timeslot ch #3 Receive Timeslot ch #0 Receive Timeslot ch #1 Receive Timeslot ch #2 Receive Timeslot ch #3 PCMW Data register PCMW Data register PCMR Data register PCMR Data register PCM Control register Tone Generation reg. Coefficient State reg. Software rev. ID code Silicon revision ID code Int. Mask I/O Port (03h) Int. Mask I/O Port (04h) Description
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STLC5048
REGISTER DESCRIPTION I/O Direction Register (DIR) Addr=00h; Reset Value=00h Addr=01h; Reset Value=X0h
BIt7 R/W IO7 Bit6 0 IO6 Bit5 0 IO5 Bit4 0 IO4 Bit3 0 IO3 Bit2 0 IO2 Bit1 0 IO1 Bit0 0 IO0
BIt7 R/W
Bit6 0
Bit5 0
Bit4 0
Bit3 0 IO11
Bit2 0 IO100
Bit1 0 IO9
Bit0 1 IO8
IO11..0=0 I/O pin 11..0 is an input, data on the I/O input is written in DATAn register bit 11..0. IO11..0=1 I/O pin 11..0 is an output, data contained in DATAn register bit 11..0 is transferred to the I/O output. I/O Data Register channel #0 (DATA0) Addr=02h; Reset Value=00h Addr=03h; Reset Value=X0h If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
BIt7 R/W D07 Bit6 0 D06 Bit5 0 D05 Bit4 0 D04 Bit3 0 D03 Bit2 0 D02 Bit1 1 D01 Bit0 0 D00
BIt7 R/W
Bit6 0
Bit5 0
Bit4 0
Bit3 0 D011
Bit2 0 D010
Bit1 1 D09
Bit0 1 D08
When CS0 is active D011..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D011..0 will be written by the values applied to those pins while CS0 is low. If bit 4 of CONF register (STA)=1 Static I/O mode:
Bit7 R/W DS7 Bit6 0 DS6 Bit5 0 DS5 Bit4 0 DS4 Bit3 0 DS3 Bit2 0 DS2 Bit1 1 DS1 Bit0 0 DS0
Bit7 R/W
Bit6 0
Bit5 0
Bit4 0
Bit3 0 DS11
Bit2 0 DS10
Bit1 1 DS9
Bit0 1 DS8
DS11..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding DS11..0 will be written by the values applied to those pins.
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STLC5048
I/O Data Register channel #1 (DATA1) Addr=04h; Reset Value=00h Addr=05h; Reset Value=X0h If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7 R/W D17 Bit6 0 D16 Bit5 0 D15 Bit4 0 D14 Bit3 0 D13 Bit2 1 D12 Bit1 0 D11 Bit0 0 D10
BIt7 R/W
Bit6 0
Bit5 0
Bit4 0
Bit3 0 D111
Bit2 1 D110
Bit1 0 D19
Bit0 1 D18
When CS1 is active D111..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D111..0 will be written by the values applied to those pins while CS1 is low. If bit 4 of CONF register (STA)=1 Static I/O mode: In static mode CS pins are used as additional I/O pins. The CIO0..3 bits are used to define the direction of these pins.
BIt7 R/W Bit6 0 Bit5 0 Bit4 0 Bit3 0 CIO3 Bit2 1 CIO2 Bit1 0 CIO1 Bit0 0 CIO0
CIO0..3=0 The CS0..3 is a static input, DATA is written in DATA2 register bits 0..3. CIO0..3=1 The CS0..3 is a static output, DATA is taken from DATA2 register bits 0..3. I/O Data Register channel #2 (DATA2) Addr=06h; Reset Value=00h Addr=07h; Reset Value=X0h If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7 R/W D27 Bit6 0 D26 Bit5 0 D25 Bit4 0 D24 Bit3 0 D23 Bit2 1 D22 Bit1 1 D21 Bit0 0 D20
Bit7 R/W
Bit6 0
Bit5 0
Bit4 0
Bit3 0 D211
Bit2 1 D210
Bit1 1 D29
Bit0 1 D28
When CS2 is active D211..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D211..0 will be written by the values applied to those pins while CS2 is low.
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STLC5048
If bit 4 of CONF register (STA)=1 Static I/O mode:
Bit7 R/W Bit6 0 Bit5 0 Bit4 0 Bit3 0 CD3 Bit2 1 CD2 Bit1 1 CD1 Bit0 0 CD0
CD0..3 are transferred to the corresponding CS pin if configured as static output (see register DATA1). For the CS pins configured as static inputs the corresponding CD0..3 will be written by the values applied to those pins. I/O Data Register channel #3 (DATA3) Addr=08h; Reset Value=00h Addr=09h; Reset Value=X0h Used only if bit 4 of CONF register (STA)=0; Dynamic I/O mode:
Bit7 R/W D37 Bit6 0 D36 Bit5 0 D35 Bit4 0 D34 Bit3 1 D33 Bit2 0 D32 Bit1 0 D31 Bit0 0 D30
Bit7 R/W
Bit6 0
Bit5 0
Bit4 0
Bit3 1 D311
Bit2 0 D310
Bit1 0 D39
Bit0 1 D38
When CS3 is active D311..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D311..0 will be written by the values applied to those pins while CS3 is low. If bit4 of CONF register (STA) = 1 Static I/O mode: D33..0=1: The corresponding CSn cannot generate interrupt. D33..0=0: The corresponding I/O (programmed as input) can generate interrupt if a change of status is detected. Persistency Check Register (PCHK-A/B) Addr=0Ah; Reset Value=00h Addr=0Bh; Reset Value=00h Two input signal per channel, labelled A and B, are submitted to persistency check. In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the multiplexed lines IO0 (pin 13) and IO1 (pin 14). In static mode (STA=1) persistency check is performed on four pairs of lines, assigned to each channel according to the table:
CHAN # 0 1 2 3 Input A IO0 (pin 19) IO4 (pin 17) IO6 (pin 48) IO10 (pin 44) Input B IO1 (pin 14) IO5 (pin 18) IO7 (pin 47) IO11 (pin 43)
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STLC5048
Bit7 R/W TA7
Bit6 0 TA6
Bit5 0 TA5
Bit4 0 TA4
Bit3 1 TA3
Bit2 0 TA2
Bit1 1 TA1
Bit0 0 TA0
Bit7 R/W TB7
Bit6 0 TB6
Bit5 0 TB5
Bit4 0 TB4
Bit3 1 TB3
Bit2 0 TB2
Bit1 1 TB1
Bit0 1 TB0
TA7..0 and TB7..0, contents of PCHKA and PCHKB registers, define the minimum duration of input A and B to generate interrupt; spurious transitions shorter than the programmed value are ignored. The time width can be calculated according to the formula: Time - Width A = (TA7..0)*64s Time - Width B = (TB7..0)*64s If PCHKA/B is programmed to 00h the persistency check is not performed and any detected transition will generate interrupt. All the inputs, with or without persistency check, are sampled with a repetition rate of 32s. Interrupt Register (INT) Addr=10h; Reset Value=00h Read Only
Bit7 1 Bit6 0 ITV Bit5 0 IPCM Bit4 1 ICKF Bit3 0 ID3 Bit2 0 ID2 Bit1 0 ID1 Bit0 0 ID0
In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related channel (SLIC). Any single bit IDn is cleared after reading related I/O register or by setting MCn bit High (i.e. when channel n is disabled to generate interrupt). In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and CS3..0 respectively: ID0: is set High when the interrupt is requested from any the I/O11..0 lines. ID2: is set High when the interrupt is requested from any the CS3..0 (configured as I/O). ID0 and ID2 are cleared after reading related I/O register. ID1 and ID3 are don't care. ITV = 1: If the interrupt has been generated by time-out violation on the MCU serial interface. IPCM = 1: When transmit PCM data reading/writing test is enabled an interrupt is generated every time valid data are available (RRD bit set to 1) or must be written (WRD bit set to 1). The interrupt is cleared after reading/ writing the data in the PCMRD/PCMWD register via the MCU interface. ICKF = 1: If the interrupt has been generated by a clock failure on PCM port (MCLK). The INT register is cleared after reading operation only if signals (alarm cause) are inactive.
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STLC5048
Interrupt Mask Register for I/O port (DMASK) Addr=11h; Reset Value=FFh Addr=12h; Reset Value=XFh
Bit7 R/W MD7 Bit6 0 MD6 Bit5 0 MD5 Bit4 1 MD4 Bit3 0 MD3 Bit2 0 MD2 Bit1 0 MD1 Bit0 1 MD0
Bit7 R/W
Bit6 0
Bit5 0
Bit4 1
Bit3 0 MD11
Bit2 0 MD10
Bit1 1 MD9
Bit0 0 MD8
MD11..0=1: The corresponding I/O doesn't generate interrupt. MD11..0=0: The corresponding I/O (programmed as input) generate interrupt if a change of status is detected. Input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check register PCHKA/B. Line without persistency check generate an immediate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt. Interrupt Mask Register for Interrupt (IMASK) Addr=13h; Reset Value=FFh
Bit7 R/W x Bit6 0 MTV Bit5 0 MPCM Bit4 1 MCF Bit3 0 MC3 Bit2 0 MC2 Bit1 1 MC1 Bit0 1 MC0
For dynamic I/O configuration, MCn bits are the disable/enable interrupt related to the channel n. MC3..0=1: Any I/O line of the related channel #n is disabled to generate interrupt independently of DMASK setting. MC3..0=0: Any I/O line of the related channel #n is enabled to generate interrupt depending on DMASK setting. For static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are configured as I/O lines. MC0=1: The corresponding I/O cannot generate interrupt independently of DMASK setting. MC0=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DMASK setting. MC2=1: The corresponding I/O cannot generate interrupt independently of DATA3_L setting (bit 3..0). MC2=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DATA3_L setting (bit 3..0). MC3 and MC1 bit are not used in static mode. Input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check register PCHKA/B. Line without persistency check generate an immediate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt MCF=1: The corresponding alarm bit (CKF) doesn't generate interrupt. MCF=0: The corresponding alarm bit (CKF) can generate interrupt. MTV=1: The corresponding alarm bit (TV) doesn't generate interrupt. MTV=0: The corresponding alarm bit (TV) can generate interrupt. MPCM =1 : The IPCM interrupt is masked (generation disabled). MPCM =0 : The IPCM interrupt is enabled (generation enabled).
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STLC5048
Alarm Register (ALARM) Addr=14h; Reset Value=01h Read Only
Bit7 1 0 Bit6 0 0 Bit5 0 0 Bit4 1 0 Bit3 0 0 Bit2 1 0 Bit1 0 0 Bit0 0 POR
POR=0: No Power On Reset is detected during operation. POR=1: A Power On Reset is detected during operation. The ALARM register is cleared after reading operation only if signals (alarm cause) are inactive. Configuration Register (CONF) Addr=20h; Reset Value=BFh
BIt7 R/W RES Bit6 0 LIN Bit5 1 AMU Bit4 0 STA Bit3 0 PD3 Bit2 0 PD2 Bit1 0 PD1 Bit0 0 PD0
RES=0 Normal Operation RES=1 Device Reset: I/0n and Csn are all inputs, DX is H.I. (equivalent to Hw reset). LIN=0 A or law PCM encoding LIN=1 Linear encoding (16 bits), two's complement. AMU=0 law selection (all bits inverted) AMU=1 A law selection (even bits inverted) STA=0 CS0 to CS3 scan the four SLICs connected to the I/O control port, each CS has a 31.25s repetition time. STA=1I/O are static, CS0 to CS3 are configured as generic static I/O PD3..0=0 Codec 3..0 is active PD3..0=1 Codec 3..0 is in Power Down. When one codec is in Power Down the corresponding VFRO output is set to AGND and the corresponding transmit time slot on DX is set in H.I. Command Enable register (COMEN) Addr=21h; Reset Value=80h
Bit7 R/W PDR Bit6 0 0 Bit5 1 0 Bit4 0 0 Bit3 0 E3 Bit2 0 E2 Bit1 0 E1 Bit0 1 E0
The En bits enable a command on one or more channels. All enabled channels will receive the entered data. At least one channel must be enabled before every command. E0..3=0: commands disabled on the corresponding channel 0..3 E0..3=1: commands enabled on the corresponding channel 0..3 PDR = 0: RAM is enabled also in Power Down. PDR = 1: RAM is disabled in Power Down. In this way it's possible to reduce the power consumption in Power Down.
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STLC5048
Synchronous Check register (SYNCK) Addr=23h; Reset Value=E4h Read Only
Bit7 1 1 Bit6 0 1 Bit5 1 1 Bit4 0 0 Bit3 0 0 Bit2 0 1 Bit1 1 0 Bit0 1 0
This register contains a fixed code (E4h) that can be read to check the synchronisation of the MCU interface. DSP Status Register (CTRLACK) Addr=25h; Reset Value=01h Read Only
Bit7 1 0 Bit6 0 0 Bit5 1 0 Bit4 0 0 Bit3 0 0 Bit2 1 0 Bit1 0 INIT Bit0 1 CKEND
CKEND bit is 0 while the checksum calculation is performed: in the other time is always set to 1. INIT bit becomes active (INIT = 1) after the DSP initialization. Normally it requires 70 us after the reset to be set to 1. Checksum register (CKSUM) Addr=26h; Reset Value=00h Addr=27h; Reset Value=00h Read Only
Bit7 1 CK7 Bit6 0 CK6 Bit5 1 CK5 Bit4 0 CK4 Bit3 0 CK3 Bit2 1 CK2 Bit1 1 CK1 Bit0 0 CK0
Bit7 1 CK15
Bit6 0 CK14
Bit5 1 CK13
Bit4 0 CK12
Bit3 0 CK11
Bit2 1 CK10
Bit1 1 CK9
Bit0 1 CK8
The cheksum value is calculated every time the CKSTART instruction is performed and the result is available after a proper delay (max 400 s). This register contains the cheksum value calculated on the contents of the following coefficient (each of 16 bits): ZERO KDF0_0 KDF0_1 KDF0_2 KDF1_0 KDF1_1 KDF1_2 KDF2_0 KDF2_1 KDF2_2 KDF3_0 KDF3_1 KDF3_2 AFE_CFF GRX0 GTX0 RFC0_0 ...... RFC0_16 XFC0_0 ...... XFC0_16 BFC0_0 ...... BFC0_25 ZFC0_0 ...... ZFC0_4 GRX1 GTX1 RFC1_0 ...... RFC1_16 XFC1_0 ...... XFC1_16 BFC1_0 ......BFC1_25 ZFC1_0 ...... ZFC1_4 GRX2 GTX2 RFC2_0 ......RFC2_16 XFC2_0 ...... XFC2_16 BFC2_0 ...... BFC2_25 ZFC2_0 ...... ZFC2_4 GRX3 GTX3 RFC3_0 ...... RFC3_16 XFC3_0 ...... XFC3_16 BFC3_0 ...... BFC3_25 ZFC3_0 ......ZFC3_4
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STLC5048
Loopback Register (LOOPB) Addr=2Ah; Reset Value=00h
Bit7 R/W DL3 Bit6 1 DL2 Bit5 0 DL1 Bit4 1 DL0 Bit3 1 AL3 Bit2 0 AL2 Bit1 1 AL11 Bit0 0 AL0
DL3..0=0: Normal Operation DL3..0=1: Codec #3..0 is set in Digital Loopback mode, this means that the receive PCM signal applied to the programmed Receive Time Slot is transferred to the programmed Transmit Time Slot. AL3..0=0: Normal Operation AL3..0=1: Codec #3..0 is set in Analog Loopback mode, this means that the VFRO signal is transferred to the VFXI input internally into the Codec. When loopbacks are enabled the signal appears also at the corresponding VFRO output. It is possible to have no signal on the VFRO output programming the GRX command to 00h in case of digital loopback. Transmit Preamplifier Gain Register (TXG) Addr=2Bh; Reset Value=00h
Bit7 R/W Bit6 0 Bit5 1 Bit4 0 Bit3 1 TG3 Bit2 0 TG2 Bit1 1 TG1 Bit0 1 TG0
TG3..0=0: Transmit preamplifier gain ch. 3..0 = 0dB TG3..0=1: Transmit preamplifier gain ch. 3..0 = 3.52dB Overall transmit gain depends on combination of TXG and GTXn registers. Receive Amplifier Gain Register (RXG) Addr=2Ch; Reset Value=00h
Bit7 R/W R31 Bit6 0 R30 Bit5 1 R21 Bit4 0 R20 Bit3 1 R11 Bit2 1 R10 Bit1 0 R01 Bit0 0 R00
Rn0=0,Rn1=0: Receive amp. gain ch #n = mute Rn0=1,Rn1=0: Receive amp. gain ch #n = -12dB Rn0=0,Rn1=1: Receive amp. gain ch #n = -6dB Rn0=1,Rn1=1: Receive amp. gain ch #n = 0dB Overall receive gain depends on the receive amplifier gain (R3..0) setting in RXG reg. and digital gain (GRXn reg. setting).
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STLC5048
SLIC Line Current Limit reg (ILIM) Addr=2Dh; Reset Value=00h
Bit7 R/W 0 Bit6 0 0 Bit5 1 0 Bit4 0 D4 Bit3 1 D3 Bit2 1 D2 Bit1 0 D1 Bit0 1 D0
D4..0 = 0: Programmed value is 53 D4..0 = 1: Programmed value is 2 The step is 1.6 mA This register allows to program a line current limitation from 2 to 53mA with a step equal to 1.6mA. These values can be obtained using an external 15KOhm resistor in kit with STLC3080. SLIC Off-Hook threshold register (ITH) Addr=2Eh; Reset Value=00h
Bit7 R/W 0 Bit6 0 0 Bit5 1 0 Bit4 0 En Bit3 1 D3 Bit2 1 D2 Bit1 1 D1 Bit0 0 D0
D3..0 = 0: Programmed value is 16 mA D3..0 = 1: Programmed value is 1 mA The step is equal to 1 mA. En = 1 The DC SLIC programmability block is enabled (ITH and ILIM) En = 0 The DC SLIC programmability block is disabled (ITH and ILIM) This register allows to program a threshold value from 1 to 16 mA with a step equal to 1mA. These values can be obtained using an external 12.5KOhm resistor in kit with STLC3080. PCM Shift Register (PCMSH) Addr=50h; Reset Value=00h
Bit7 R/W Bit6 1 XS2 Bit5 0 XS1 Bit4 1 XS0 Bit3 0 Bit2 0 RS2 Bit1 0 RS1 Bit0 0 RS0
XS2..0:Effective start of the TX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge. RS2..0:Effective start of the RX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge. PCM Command register (PCMCOM) Addr=51h; Reset Value=00h
Bit7 R/W RR Bit6 1 WR Bit5 0 PC1 Bit4 1 PC0 Bit3 0 TE Bit2 0 RPAB Bit1 0 TPB Bit0 1 TPA
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STLC5048
TPA/B = These two bits are used to enable the DX outputs of the port A or/and B. According to the combination of these two bits the enabled port will be as follows:
TPB 0 0 1 1 TPA 0 1 0 1 Description Both Ports disabled Port A enabled Port B enabled Both ports enabled
RPAB = 0: Port A enabled (DRA input selected) RPAB = 1: Port B enabled (DRB input selected) TE = 0: Transmit PCM data change on rising edge of MCLK TE = 1: Transmit PCM data change on falling edge of MCLK PC1-PC0 = Selection of the channel for the PCM access data via MCU.
PC0 0 1 0 1 PC1 0 0 1 1 Description Channel #0 selected Channel #1 selected Channel #2 selected Channel #3 selected
WR = 1: Setting this bit , receive PCM data writing via MCU (after A/ decoding) is enabled on selected channel and IPCM interrupt is generated every time FS signal becomes active, together to the set of the WRD bit in the PCMCTRL register. A data byte must be written every 125s, if data is not replaced the old value is inserted again but the PMW bit is set to 1 in the PCMCTRL register. RR = 1: Setting this bit, transmit PCM data reading (after A/ encoding) via MCU is enabled on selected channel and IPCM interrupt is generated every time that data are available, together to the set of the RRD bit in the PCMCTRL register. A data byte must be read every 125S, if data is not read the new value is written in the PCM access register but the POW bit is set to 1 in the PCMCTRL register. Transmit Time Slot ch #0 (DXTS0) Addr=52h; Reset Value=00h
Bit7 R/W EN0 Bit6 1 T06 Bit5 0 T05 Bit4 1 T04 Bit3 0 T03 Bit2 0 T02 Bit1 1 T01 Bit0 0 T00
EN0=0:Selected transmit time slot on DX output is in H.I. EN0=1:Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI0. T06..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot. Example: if T06..T00=00:
TS0 15 14 13 12 11 10 9 8 7 6 5 4 TS1 3 2 1 0
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STLC5048
Transmit Time Slot ch #1 (DXTS1) Addr=53h; Reset Value=00h
Bit7 R/W EN1 Bit6 1 T16 Bit5 0 T15 Bit4 1 T14 Bit3 0 T13 Bit2 0 T12 Bit1 1 T11 Bit0 1 T10
EN1=0: Selected transmit time slot on DX output is in H.I. EN1=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI1. T16..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI1 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot. Example: if T16..T10=00:
TS0 15 14 13 12 11 10 9 8 6 5 4 3 TS1 7 2 1 0
Transmit Time Slot ch #2 (DXTS2) Addr=54h; Reset Value=00h
Bit7 R/W EN2 Bit6 1 T26 Bit5 0 T25 Bit4 1 T24 Bit3 0 T23 Bit2 1 T22 Bit1 0 T21 Bit0 0 T20
EN2=0: Selected transmit time slot on DX output is in H.I. EN2=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI2. T26..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI2 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot. Example: if T26..T20=00:
TS0 15 14 13 12 11 10 9 8 6 5 4 3 TS1 7 2 1 0
Transmit Time Slot ch #3 (DXTS3) Addr=55h; Reset Value=00h
Bit7 R/W EN3 Bit6 1 T36 Bit5 0 T35 Bit4 1 T34 Bit3 0 T33 Bit2 1 T32 Bit1 0 T31 Bit0 1 T30
EN3=0: Selected transmit time slot on DX output is in H.I. EN3=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI3. T36..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI3 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot.
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STLC5048
Example: if T36..T30=00:
TS0 15 14 13 12 11 10 9 8 6 5 4 3 TS1 7 2 1 0
Receive Time Slot ch #0 (DRTS0) Addr=56h; Reset Value=00h
Bit7 R/W EN0 Bit6 1 R06 Bit5 0 R05 Bit4 1 R04 Bit3 0 R03 Bit2 1 R02 Bit1 1 R01 Bit0 0 R00
EN0=0: Disable reception of selected time slot. EN0=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO0 output. R06..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred to VFRO0 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot. Example: if R06..R00=00:
TS0 15 14 13 12 11 10 9 8 6 5 4 3 TS1 7 2 1 0
Receive Time Slot ch #1 (DRTS1) Addr=57h; Reset Value=00h
Bit7 R/W EN1 Bit6 1 R16 Bit5 0 R15 Bit4 1 R14 Bit3 0 R13 Bit2 1 R12 Bit1 1 R11 Bit0 1 R10
EN1=0: Disable reception of selected time slot. EN1=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO1 output. R16..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred to VFRO1 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot. Example: if R16..R10=00:
TS0 15 14 13 12 11 10 9 8 6 5 4 3 TS1 7 2 1 0
Receive Time Slot ch #2 (DRTS2) Addr=58h; Reset Value=00h
Bit7 R/W EN2 Bit6 1 R26 Bit5 0 R25 Bit4 1 R24 Bit3 1 R23 Bit2 0 R22 Bit1 0 R21 Bit0 0 R20
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STLC5048
EN2=0: Disable reception of selected time slot. EN2=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO2 output. R26..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred to VFRO2 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot. Example: if R26..R20=00:
TS0 15 14 13 12 11 10 9 8 6 5 4 3 TS1 7 2 1 0
Receive Time Slot ch #3 (DRTS3) Addr=59h; Reset Value=00h
Bit7 R/W EN3 Bit6 1 R36 Bit5 0 R35 Bit4 1 R34 Bit3 1 R33 Bit2 0 R32 Bit1 0 R31 Bit0 1 R30
EN3=0: Disable reception of selected time slot. EN3=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO3 output. R36..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred to VFRO3 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot. Example: if R36..R30=00:
TS0 15 14 13 12 11 10 9 8 6 5 4 3 TS1 7 2 1 0
PCMW Data Register (PCMWD) Addr=5Ah; Reset Value=00h Addr=5Bh; Reset Value=00h
Bit7 R/W D7 Bit6 1 D6 Bit5 0 D5 Bit4 1 D4 Bit3 1 D3 Bit2 0 D2 Bit1 1 D1 Bit0 0 D0
Bit7 R/W D15
Bit6 1 D14
Bit5 0 D13
Bit4 1 D12
Bit3 1 D11
Bit2 0 D10
Bit1 1 D9
Bit0 1 D8
This register is used to write receive PCM data via the MCU interface. Writing this register the IPCM interrupt (if generated only by writing access) is automatically cleared. In A/ law only the first 8 bit are used. In linear code option both registers must be used.
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STLC5048
PCMR Data Register (PCMRD) Addr=5Ch; Reset Value=00h Addr=5Dh; Reset Value=00h Read only
Bit7 1 D7 Bit6 1 D6 Bit5 0 D5 Bit4 1 D4 Bit3 1 D3 Bit2 1 D2 Bit1 0 D1 Bit0 0 D0
Bit7 1 D15
Bit6 1 D14
Bit5 0 D133
Bit4 1 D12
Bit3 1 D11
Bit2 1 D10
Bit1 0 D9
Bit0 1 D8
This register is used to read transmit PCM data via the MCU interface. Reading this register the IPCM interrupt (if generated only by reading access) is automatically cleared. In A/ law only the first 8 bit are used. In linear code option both registers must be read, first the LSB and after the MSB. PCM Control Register (PCMCTRL) Addr= 5Eh; Reset Value=00h Read only
Bit7 1 Bit6 1 Bit5 0 Bit4 1 Bit3 1 RRD Bit2 1 WRD Bit1 1 POW Bit0 0 PMW
PMW = 1: Data is not written every FS while writing PCM access data is enabled. POW = 1: Data is not read every FS while reading PCM access data is enabled. WRD = 1: Device is waiting for PCM data insertion in PCMWD register. The bit is reset after writing at least one byte. RRD = 1: Data are available on PCMRD register. The bit is reset after reading the two bytes of the register (first the LSB and after the MSB). Tone Generation register (TONEG) Addr=60h; Reset Value=00h
Bit7 R/W T31 Bit6 1 T30 Bit5 1 T21 Bit4 0 T20 Bit3 0 T11 Bit2 0 T10 Bit1 0 T01 Bit0 0 T00
Tn0=0,Tn 1=0: No tone is generated on ch #n Tn0=1,Tn 1=0: A tone with 25Hz frequency is generated on ch #n. Tn0=0,Tn 1=1: A tone with 1KHz frequency is generated on ch #n. Tn0=1,Tn 1=1: A tone with 3KHz frequency is generated on ch #n. This register allows the generation of a tone in the RX direction.
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STLC5048
Coefficient State register (COEFST) Addr= 61h; Reset Value=F0h
Bit7 R/W FD3 Bit6 1 FD2 Bit5 1 FD1 Bit4 0 FD0 Bit3 0 FR3 Bit2 0 FR2 Bit1 0 FR1 Bit0 1 FR0
FR0..3=1: All channel filters and gain blocks are configured as defined in the ringing state FR0..3=0: All channel filters and gain blocks are configured as defined with the programmed value if also the corresponding FD bit is set to 0 FD0..3=1: All channel filters and gain blocks are configured as defined in the default state if also the corresponding FR bit is set to 0 FD0..3=0: All channel filters and gain blocks are configured as defined with the programmed value if also the corresponding FR bit is set to 0 Software Revision ID Code (SWRID) Addr=70h; Read only.
Bit7 1 0 Bit6 1 0 Bit5 1 0 Bit4 1 1 Bit3 0 0 Bit2 0 1 Bit1 0 0 Bit0 0 0
This register contains the DSP Software revision Code identifier. Hardware Revision ID Code (HWRID) Addr=71h; Read only.
Bit7 1 0 Bit6 1 0 Bit5 1 0 Bit4 1 0 Bit3 0 0 Bit2 0 0 Bit1 0 0 Bit0 1 1
This register contains the Silicon revision Code identifier. SINGLE BYTE INSTRUCTION
Name REACOM CKSTART Description Realignment command Start Checksum ID 28h 29h
Realignment Command (REACOM) This single instruction is used to realign the MCU interface in case of out of synchronisation. This instruction must be executed Nmax+1 times to be successfull.
Bit7 0 Bit6 0 Bit5 1 Bit4 0 Bit3 1 Bit2 0 Bit1 0 Bit0 0
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STLC5048
Start Checksum Calculation (CKSTART) This single instruction is used to start the checksum calculation of the enetered data used to configure the device.
Bit7 0 Bit6 0 Bit5 1 Bit4 0 Bit3 1 Bit2 0 Bit1 0 Bit0 1
COMMAND LIST
Name BLKEN KDF AFECFF T_OUT GRX GTX RFC XFC BFC ZFC Description Block enable KD Filter AFE KA Coefficient (*) Timeout value (*) Receive Gain Transmit Gain R Filter Coefficient X Filter Coefficient B Filter Coefficient Z Filter Coefficient ID 22h 30h 31h 32h 40h 41h 42h 43h 44h 45h
(*) For this two commands the bit set in the COMEN register are not considered.
COMMAND DESCRIPTION Each command is transferred on every channel that has the proper bit in the COMEN register set to 1. Block Enable command (BLKEN) Reset Value=00h The command is used to enable/disable the B, Z, R and X blocks
Bit7 R/W Bit6 0 Bit5 1 Bit4 0 Bit3 0 XE Bit2 0 RE Bit1 1 ZE Bit0 0 BE
BE=1: The B block is equal to an open circuit BE=0: The B block is configured as defined in the Ringing state or with the programmed value ZE=1: The Z block is equal to an open circuit ZE=0: The Z block is configured as defined in the Ringing state or with the programmed value RE=1: The R block is equal to a short circuit RE=0: The R block is configured as defined in the Ringing state or with the programmed value XE=1: The X block is equal to a short circuit XE=0: The X block is configured as defined in the Ringing state or with the programmed value
29/45
STLC5048
KD Filter (KDF) The register is used to set the 3 coefficients (each of 16 bits) of the KD filter of the channel #n.
Bit7 R/W Bit6 0 Bit5 1 Bit4 1 Bit3 0 Bit2 0 Bit1 0 Bit0 0
. ..
AFE Coefficient (AFE_CFF) Reset value = AA00h
Bit7 R/W KA31 Bit6 0 KA30 Bit5 1 KA21 Bit4 1 KA20 Bit3 0 KA11 Bit2 0 KA10 Bit1 0 KA01 Bit0 1 KA00 TTX
KAn0, KAn1 = KA coefficient for Ch #n According to the value of each couple of bits, the KA block is set in the following condition: KAn1 KAn0 0 1 1 X 0 1 KA block disabled KA set for low gain KA set for high gain
When the application involves also the metering pulse signal the AFE of the STLC5048 must be adapted in order to manage also this signal. For this purpose is provided the TTX bit. TTX = 0: the current application is not using the metering pulse signal TTX = 1: the current application is using the metering pulse signal Timeout value (T_OUT) Reset Value=FFFFh
Bit7 R/W T7 T15 Bit6 0 T6 T14 Bit5 1 T5 T13 Bit4 1 T4 T12 Bit3 0 T3 T11 Bit2 0 T2 T10 Bit1 1 T1 T9 Bit0 0 T0 T8
Reset value = Maximum value = FFFFh (2048 us) To disable this function the T0 bit must be set to 0. To enable this function the T0 bit must be set to 1; the time-out value is set by means of T<15..1> bits. Time_out = (T_OUT[15:1]*62.5 + 31.24)ns The minimum step is 62.5 ns.
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STLC5048
Receive Gain (GRX)
Bit7 R/W Bit6 1 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 0 Bit0 0
00h: Stop any received signal to reach the VFRO0 analog output. In order to open the impedance synthesis feedback it's necessary to mute the RX analog amplifier, as well. >00h: Digital gain is inserted in the RX path equal to: 20Log[prog.value/32768] The prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7FFFh. Transmit Gain (GTX)
Bit7 R/W Bit6 1 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 0 Bit0 1
00h:
Stop any transmit signal, null level is transmitted in the corresponding timeslot on DX output.
>00h: Digital gain is inserted in the TX path equal to: 20Log[prog.value/32768] The prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7FFFh. R Filter Coefficient (RFC) The register is used to set the 17 coefficients (each of 16 bits) of the R filter of the channel #n.
Bit7 R/W Bit6 1 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 1 Bit0 0
. .
X Filter Coefficient (XFC) The register is used to set the 17 coefficients (each of 16 bits) of the X filter of the channel #n.
Bit7 R/W Bit6 1 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 1 Bit0 1
. .
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STLC5048
B Filter Coefficient (BFC) The register is used to set the 26 coefficients (each of 16 bits) of the B filter of the channel #n.
Bit7 R/W Bit6 1 Bit5 0 Bit4 0 Bit3 0 Bit2 1 Bit1 0 Bit0 0
. .
Z Filter Coefficient (ZFC) The register is used to set the 5 coefficients (each of 16 bits) of the Z filter of the channel #n.
Bit7 R/W Bit6 1 Bit5 0 Bit4 0 Bit3 0 Bit2 1 Bit1 0 Bit0 1
. .
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STLC5048
ELECTRICAL CHARACTERISTCS Typical value are for 25C and nominal supply voltage. Minimum and maximum values are guaranteed over the temperature 0-70C range by production testing and supply voltage range shown in the Operating Ranges. Performances over -40 +85C range are guaranteed by product characterisation unless otherwise specified.
Symbol DIGITAL INTERFACE Vil Vih Iil Iih Ci Vol Voh Input Voltage Low DI pins Input Voltage High DI pins Input Current Low DI pins Input Current High DI pins Input Capacitance (all dig. inp.) Output Voltage Low DX, TSX pins Iol=3.2mA (other pins Iol=1mA) Output Voltage High DX pin Ioh=-3.2mA (other pins Iol=1mA) 0 0.85Vdd 0 0.8Vdd -10 -10 5 0.4 Vdd 0.2Vdd 5.5 10 10 V V A A pF V V Parameter Test Condition Min. Typ. Max. Unit
Note: all digital input are 5V tolerant.
ANALOG INTERFACE RIX ROR Idd(pd) Idd(act) f(MCLK) Transmit Input Amplifier Input Impedance (VFXI) Receive Output Impedance Power down Current Active Current Master Clock Frequency 1 1 10 55 1.536 1.544 2.048 4.096 8.192 38 38 10 10 10 10 15 15 40 15 15 70 M mA mA MHz
POWER DISSIPATION
PCM INTERFACE TIMING
Twmh Twml Trm Tfm Thbf Tsfb Tdmd Tdmz Tdfd
Period of MCLK high Period of MCLK low MCLK rise time MCLK fall time Hold Time MCLK Low to FSX/R High or Low Setup time FSX/R High to MCLK Low Delay Time, MCLK High to Data Valid Delay Time from MCLK(8) Low to Data Output disabled Delay Time, FSX High to Data Valid if FSX rises later than MCLK rising edge Delay Time, from MCLK and FSX both high to TSX Low Delay time from MCLK(8) low to TSX disabled Setup time, DR Valid to MCLK Low Hold time, MCLK Low to DR invalid
ns ns ns ns ns ns ns ns ns
Tdmt Tzmt Tsdm Thdm
20 15 5 5 40
ns ns ns ns
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STLC5048
ELECTRICAL CHARACTERISTCS (continued) Figure 4.
TFM TRM MCLK THBF TSFB FSX TDFD TDMD DX TDMT TSX TSFB THBF FSR THDM TSDM DR 7 6 5 4 3 2 1 0
D94TL157
TWMH 8 9 10 TWML
1
2 THBF
3
4
5
6
7
TZMT 6 5 4 3 2 1 0 TZMT
7 TDMT
THBF
SERIAL CONTROL PORT TIMING Symbol fcclk twch twcl trc tfc thcs thsc tssc tdsd tcso tsdc thcd tdcd tddz Parameter Frequency of CCLK Period of CCLK High Period of CCLK Low Rise time of CCLK Fall time of CCLK Hold time, CCLK low to CS low Hold time, CCLK low to CS high Setup time, CS transition to CCLK Low Delay time, CS low to CO data valid CS off time Setup time, CI. Data in to CCLK low Hold time, CCLK low to CI invalid Delay time, CCLK low to CO Data Out Valid Delay Time, CS or CCLK9 high to CO high impedance Pull up resistor = 1KOhm Cload = 30pF 5 10 10 30 30 Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL 10 10 10 20 40 40 20 20 Test Condition Min. Typ. Max. 8 Unit MHz ns ns ns ns ns ns ns ns us ns ns ns ns
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STLC5048
ELECTRICAL CHARACTERISTCS (continued) Figure 5.
tRC CCLK tHCS CS 1 tSSC 2 3 4
tFC 5 6 7 tHSC 8 tSCS
tWCH
tWCL
tSDC CI 7 6 5 4 3 2
tHCD 1 0
tCSO tDSD 7 6 5 4 tDCD 3 2 1
CO
D00TL471
SLIC CONTROL INTERFACE TIMING (dynamic configuration) Symbol Tcs tcsw tdcsl tscsh tscsh thcsh Parameter Chip Select repetition rate Chip select pulse width Data out valid to CS low Data out held after CS high Set up time Data in to CS high Hold time data in to CS high Test Condition Min. Typ. 31.25 3.9 1.95 1.95 50 10 Max. Unit s s ns ns ns ns
Figure 6. SLIC Control port timing
tDIV tDOA tDII tDON 31.25s (32KHz)
CS1
CS2
CS3
CS4
IO (OUT)
OUT CH0
OUT CH1
OUT CH2
OUT CH3
OUT CH0
OUT CH1
IO (IN)
IN CH0
IN CH1
IN CH2
IN CH3
IN CH0
IN CH1
D99TL460
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STLC5048
ELECTRICAL CHARACTERISTICS (continued)
TRANSMIT TRANSFER CHARACTERISTICS (all tests are performed in absolute gain condition (TXG = GTXn = 0dB) unless otherwise specified). Symbol Parameter Absolute level at 0 dBm0 are: TXG = 0dB, GTXn = 0dB GXA GXAG GFX Transmit gain Absolute accuracy Transmit gain variation with programmed gain (within 3 dB from max dig. level) Gain variation with frequency (relative to gain at 1004Hz); 0dBm0 input signal 50 Hz 60Hz 200Hz 300-3000Hz 3400Hz 4000Hz 4600Hz and above GAXT GAXE GTX Gain variation with temperature Gain variation with Supplies +/- 5% 0dBm0 Input Signal Gain Tracking with Tone (1004Hz Mu Law, 820Hz A Law) (1) -20 -20 0 0.15 0 -14.0 -32.0 0.10 0.05 dB dB dB GSX = 3 to -40dBm0 GSX = -40 to -50dBm0 GSX = -50 to -55dBm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 dB VFXI = +3dbm0 VFXI = 0 to -30dBm0 VFXI = -40 dBm0 VFXI = -50 to -55 dBm0 NCT NPT DAX DPXM DPXA GSPX Transmit Noise C Message Weighted (Mu and A Law) Transmit Noise Psophometric Weighted @ 0dBr, Zadm=600Ohm (2) Absolute Delay (3) Single Frequency Distortion (Mu Law 0dBm0 Sinewave @ 1004Hz) Single Frequency Distortion (A Law 0dBm0 Sinewave @ 820Hz) Out of Band Spurious Noise 61mVrms at VFXI 4200Hz to 72kHz B = 0, Z = 0, X = R = 1 462 33 36 30 15 12 -68 587 -46 dB -46 -39 dBm0 dBrnCo dBm0p S dB -0.15 -0.2 Test Condition Min. Typ. 60 0.15 0.2 Max. Unit mVrms dB dB dB
-1.8 -0.15 -0.7
-0.10 -0.05
QDX
Quantization Distortion with Tone (1004Hz Mu Law, 820Hz ALaw)
(1) VFXI=106mVrms, TXG=+3.52dB, GTX=-8.308dB (levels and gain condition eqivalent to 0dBr with Zadm = 600 Ohm on the application) (2) TXG=+3.52dB, GTX=-8.308dB (gain condition eqivalent to 0dBr with Zadm = 600 Ohm on the application) (3) The max value includes 125sec for the time slot synchronization
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STLC5048
ELECTRICAL CHARACTERISTICS (continued)
RECEIVE TRANSFER CHARACTERISTICS (all tests are performed in absolute gain condition (RXG = GRXn = 0dB) unless otherwise specified). Symbol Parameter Absolute levels at 0 dBm0 are: RXG = 0dB, GRXn = 0dB GRA GRAG Transmit gain Absolute accuracy Receive Gain Variation with programmed gain (within 3 dB from max dig. level) Gain variation with frequency (relative to gain at 1004Hz); 0dBm0 input signal Below 200Hz 200Hz 300-3000Hz 3400Hz 4000Hz GART GARE Gain variation with temperature Gain variation with Vcc=Vdd= 3.3V +/- 5% 0dBm0 Input Signal Gain Tracking with Tone (1004Hz Mu Law, 820Hz ALaw) DR = 3 to -40dBm0 DR = -40 to -50dBm0 DR = -50 to -55dBm0 QDR Quantization Distortion with Tone (1004Hz Mu Law, 820Hz ALaw) DR DR DR DR NCR NPR DAR DPR1 GSPR Receive Noise C Message Weighted (Mu Law) Receive Noise Psophometric Weighted (A Law) Absolute Delay (2) Single Frequency Distortion (0dBm0 Sinewave @ 1004Hz) Out of band spourious Noise 0dBm0 DTMF tone at DR 0dBm0 180 to 3600Hz Sinewave at DR OBN Out of Band Noise (1) Integral measure from 3.4 to 128kHz GTX = GRX = 0dB GTX = 0dB; GRX = -7dB Spectral measure from 3.4 to 200kHz in B/W = 30Hz
(1) Values related to the application including the external filter on RX. The maesure is referred to the signal replicas. (2) As note 3 at page 36
Test Condition
Min.
Typ. 547
Max.
Unit mVrms
-0.15 -0.2
0.15 0.2
dB dB
GFR
dB 0.115 0.15 0.15 0 -14 0.10 0.05 dB dB
-0.25 -0.15 -0.7 -0.10 -0.05
0 to 70 C
GTR
dB -0.2 -0.4 -1.2 0.2 0.4 1.2 dB = 3 dBm0 = 0 to -30dBm0 = -40 dBm0 = -50 to -55dBm0 33 36 30 15 8 11 -79 B = Z = 0, X = R = 1 325 450 -46 -60 -43 dB dB dBrnCo dBm0p s dB
-48 -51 -70
dBm dBm dBm
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STLC5048
ELECTRICAL CHARACTERISTCS (continued)
SUPPLY REJECTION AND CROSSTALK Symbol PSRR CTX-R CTR-X CT-ICH Parameter Power Supply Rejection Ratio 1KHz, 50mVrms Transmit to Receive Crosstalk (Input signal 200Hz to 3450Hz at 0dBm0) Receive to Transmit Crosstalk (Input signal 200Hz to 3450Hz at 0dBm0) Inter Channel Crosstalk, TX and RX direction. Input 200 to 3450 Hz at 0dBm0 at VFXI of one channel; all other VFXI inputs and all DR inputs receive idle signal. Output is measured at DX of the 3 idle channels. Input of 200 to 3450 Hz at 0dBm0 PCM at DR on ione channel. All other DR inputs and all VFXI inputs receive idle signal. Output is measured at VFRO of the 3 idle channels Test Condition 0 to 70C Min. 42 Typ. 65 -76 -76 -78 Max. Unit dB dB dB dB
Figure 7. Group Delay Distortion Mask
Delay (s) 600 500 400 Rx ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,
D02TL523
Rx direction
300 200 100
0 Delay (s) 600 500 400
500
1000
1500
2000 Tx
2500
3000
f(Hz)
Tx direction
300 200 100
,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,
500 1000 1500 2000 2500
D02TL524
0
3000
f(Hz)
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STLC5048
APPENDIX A STLC5048 absolute gains in kit with L3235N/STLC3080 Figure 8. STLC5048 in kit with STLC3080 AC application diagram.
STLC5048
DR GRX CHANNEL FILTER + VFRO RX 2 -1 ECO CANCELING Z SYNTHESIS RING RP TIP 1 RP
Zadm Iline
DX
GTX
+
CHANNEL FILTER
VFXI
TX
RS 1 RS 8200
D00TL472
CAC
ILTF
Figure 9. STLC5048 in kit with L3235N AC application diagram.
STLC5048
DR GRX CHANNEL FILTER + VFRO RX 2 -1 ECO CANCELING Z SYNTHESIS RING RP TIP 1 RP
Iline/100
RDC
Zadm Iline
DX
GTX
+
CHANNEL FILTER
VFXI
TX
RPC 1 RS 4100
D00TL473
CAC
IL
In Fig.8 is shown the application diagram of the STLC5048 in kit with the STLC3080 SLIC. The figure is related to the AC path as the STLC5048 doesn't perform any DC processing. The only DC feature performed by STLC5048 is the Off-Hook and Limitation Threshold programmability. The same application diagram for the AC processing can be applied to the kit with the L3235N (as shown in Fig. 9): the only differences are the following: The scaling factor of the Iline is 50 Rs value is 4.1 Kohm. The imoedance synthesis is fully performed by STLC5048; the L3235N SLIC (or the STLC3080) used in kit with the STLC5048 just splits the AC/DC component of Iline, scales it and traduces it into a voltage via RS. As shown in Fig. 3, the scaled current is converted into a voltage through the external resistor Rs = 4100 Ohm (8200 Ohm for the STLC3080): this value is fixed (i.e. independent on the administration): the attenuation between VLINE and VFXI is dependent on the administration. Considering the TX gain we can proceed as follows for the gain calculation: TXG = 0dB GX = 0dB
Iline/50
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STLC5048
(As reported in the absolute gain levels with 61Vrms at VFXI and GX=0dB, the DX output is 0dBm0). For instance let's calculate which TX gain to program if +4.2dBr @ 600 Ohm is to be set: VLINE = 0dBm @ 600Ohm VLIN E 1 VFXI = ------------------ ----- 4100 600 50 In case of STLC3080 the scaling factor is 100 (instead of 50) while the Rs value is 8200 (instead of 4100) so the result is the same. VLINE 1 VFXI = ------------------ --------- 8200 100 600
Refering to the formula (1), to have DX equal to 4.2dB with VLINE=0dBm GX must be set to GX = 4.2 - 4.78 = -0.58dB. Figure 10. Absolute gain in TX path.
1/100 for STLC3080 GX DX TXG VFXI RS 4100 (8200 for STLC3080) VLINE 1/50 Iline Zadm
STLC5048
VFXI = (-Iline/50)*4100 for L3235N VFXI = (-Iline/100)*8200 for STLC3080
L3235N
D00TL474
40/45
V100
GND
VCC
VCC 4.7F VRING GND VCC VDD VDD 0.1F 7 10 29 6 IL 18 1M ZA 11 D2 1N4007 RT 1M RP1 OVERVOLTAGE PROTECTION RING RP2 20 SUB ZAC 43 40 9 31 25 27 28 32 3 13 17 VSS CVSS CVCC 0.1F AGND VBAT CVB CGF 390nF 0.1F VBAT RGF 39K RR 51K CR 4.7F CF 390nF RF 39K 2 39 14 35 24 20 LIM REF GKF VPOL 34 RTF 22 BASE 44 VREG TEXT MJE350 VBAT RING 40 RP1 TX 10nF 150 38 TIP 40 D1 1N4007 CAC 100F RP2 20 TIP 100nF RX 12 CAC ZB CS 10F 10F ZS=4100 CS VSS VFRO0 2.2K 10nF 4 2 7 VA 1 6 82 5 82 3
0.1F
0.1F
0.1F
L3234
GND
VEE
VCC
DX
DR
FS
MCLK
TSX
STLC5048
IO0 CTX 100nF RNG SBY PUNEG GDK BGND VCC IO11 IO12(CS0) IO13(CS1) IO14(CS2) IO15(CS3) VFRO1 VFXI1 VFRO2 VFXI2 VFRO3 VFXI3
D98TL381B
VFXI0
L3235N
APPENDIX B
INT IO1 IO2 IO3 IO4
OH
Figure 11. STLC5048 plus L3235N/L324 kit application diagram
RES
STLC5048 Application Diagrams
CS
CCLK
SERIAL CONTROL PORTS
CO
CI
RLIM 9.1K to 35K
VCC
0.1F
VSS
STLC5048
41/45
42/45
0.1F VCC(3.3V) VDD(3.3V) VCC(5V) VCC VCC 61 60 59 58 57 20 19 18 RP1 40 RING RP1 RING RT1 RS1 RR 27 36 35 16 RT2 VREG BASE VBAT CVB VBAT 34 33 11 24 26 23 TTXIN CAC ILTF 25 RDC 30 ITH 31 RLIM 32 IREF CSRV CREV CRT CRT CREV CSRV VBAT QEXT VRING RS2 RP2 PCD VBAT LCP 1511 39 TIP RS RS 100nF RX 22 38 28 ZB IO11 10nF ZAC 14 RT RP2 TIP 150 IO10 RELR 21 VREL 12 IO9 ZAC1 9 10 29 37 13 REL1 IO8 VDD VCC AGND BGND REL0 IO7 VFRO0 33 2.2K 10nF 41 17 43 44 3 4 5 6 7 1 2 8 42 VFXI0 35 IO0 CTX 100nF GDK/AL D0 D1 D2 R0 IO6 R1 CSOUT TO OTHER SLICs CS0 28 29 53 53 VFRO1 VFXI1 VFRO2 VFXI2 TTX RDA RTTX CTTX TO OTHER SLICs CAC RTH RDC RLIM REF VFRO3 VFXI3 Components needed only for metering pulse injection TO OTHER SLICs 39 38 42 43 48 47 46 ITH ILIM CS3 CKRING CS2 CS1 RES CSIN 19 IO1 IO2 IO3 IO4 IO5 20 21 22 23 24 62 DET TX 1M MODE
STLC5048
GND
VDD
VDD
9
VEE
0.1F
VSS
8
SUB
41
DXA
DRA
11
DXB
10
DRB
15
PCM INTERFACE
FS
16
MCLK
14
13
TSX
STLC5048
STLC3080
12
M0
27
M1
54
Figure 12. STLC5048 plus STLC3080 application diagram.
INT
3
CS
CCLK
4
CO
7
SERIAL CONTROL PORTS
CI
5
6
CAP
40
CAP 0.1F
49
34
BGND and AGND must be shorthed together on the line card
VBG
D99TL459C
STLC5048
APPENDIX C Power Up Sequence The DSP after an HW (M1=0) or SW reset (CONF[7]=1) or a Power-on reset (POR) has to perform the INIT proram. To do it at least one channel must be set in active mode. After that, (2 FS are required), the INIT bit in the CTRLACK register is set to 1 and the RAM can be written and read. It must be noted that to program the device the MCLK and FS signals must be applied to the device. Following, the correct sequence that must be used in order to program the device. Power on sequence wait 5 FS signals for PLL locking CONF=BF write CONF=3F write CONF=30 wait 2 FS signals read CTRLACK=03 Check INIT bit =1 Before to start the coefficent download, one or more channels must be selected using the COMEN register. The download can be done keeping the device in Active mode (at least one channel active) or in Power Down mode (all channels in Power Down). If the second choice is selected, the PDR bit in the COMEN register must be set to 0 (internal RAM active also in Power Down mode). Sw Reset enabled after reset Sw Reset disabled All Channel Active
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STLC5048
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12
mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0(min.), 7(max.) 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011
OUTLINE AND MECHANICAL DATA
0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393
TQFP64
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
44/45
B
STLC5048
ESD - The STMicroelectronics Internal Quality Standards set a target of 2 KV that each pin of the device should withstand in a series of tests based on the Human Body Model (MIL-STD 883 Method 3015): with C = 100pF; R = 1500W and performing 3 pulses for each pin versus VCC and GND. Device characterization showed that, in front of the STMicroelectronics Internaly Quality Standards, pin 25 of STLC5048 withstand at least 1000V. The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless they must be mentionned in connection with the applicability of the different SURE 6 requirements to STLC5048.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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